`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   17:08:52 06/30/2015
// Design Name:   Etapa2
// Module Name:   D:/Libraries/Documents/Ingenieria en computacion/Arquitectura Computadoras/TrabajoFinalArquitectura/trunk/Final-Mips/Etapa2Test.v
// Project Name:  Final-Mips
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: Etapa2
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module Etapa2Test;

	// Inputs
	reg [31:0] instruccion;
	reg [31:0] E1Adder;
	reg [4:0] DestinoReg;
	reg [31:0] WriteData;
	reg RegWrite;
	reg clk;

	// Outputs
	wire RegDst;
	wire RegWriteO;
	wire ALUSrc;
	wire PCSrc;
	wire MemRead;
	wire [3:0] MemWrite;
	wire MemToReg;
	wire [1:0] ALUOp;
	wire jmp;
	wire [2:0] LoadOp;
	wire [1:0] StoreOp;
	wire [2:0] InmCtrl;
	wire [31:0] E2Adder;
	wire [31:0] ReadData1;
	wire [31:0] ReadData2;
	wire [31:0] ExtSig;
	wire [4:0] RT;
	wire [4:0] RD;

	// Instantiate the Unit Under Test (UUT)
	Etapa2 uut (
		.instruccion(instruccion), 
		.E1Adder(E1Adder), 
		.DestinoReg(DestinoReg), 
		.WriteData(WriteData), 
		.RegWrite(RegWrite), 
		.clk(clk), 
		.RegDst(RegDst), 
		.RegWriteO(RegWriteO), 
		.ALUSrc(ALUSrc), 
		.PCSrc(PCSrc), 
		.MemRead(MemRead), 
		.MemWrite(MemWrite), 
		.MemToReg(MemToReg), 
		.ALUOp(ALUOp), 
		.jmp(jmp), 
		.LoadOp(LoadOp), 
		.StoreOp(StoreOp), 
		.InmCtrl(InmCtrl), 
		.E2Adder(E2Adder), 
		.ReadData1(ReadData1), 
		.ReadData2(ReadData2), 
		.ExtSig(ExtSig), 
		.RT(RT), 
		.RD(RD)
	);

	initial begin
		// Initialize Inputs
		instruccion = 0;
		E1Adder = 0;
		DestinoReg = 0;
		WriteData = 0;
		RegWrite = 0;
		clk = 0;

		// Wait 100 ns for global reset to finish
		#100;
		// Add stimulus here
		//Primero cargamos algunos datos
		WriteData = 32'h FFFF0000;
		RegWrite = 1;
		#5
		DestinoReg = 1;
		WriteData = 32'h 0000FFFF;
		RegWrite = 1;
		#5
		RegWrite = 0;
		
		//Ahora Podes leer
		instruccion = 32'b 00000000000000010001000000100000; //ADD
		#100;
		instruccion = 32'b 00100000000011010000000000010110; //ADDI
		#100;
		instruccion = 32'b 00100000000010100000000000001111;
		#100;
		instruccion = 32'b 00100000000010110000000000001010;
	end
	
 always begin
#2; clk = ~clk;
end 
endmodule

